1. Field of the Invention
The present invention relates to interposer substrates, and, more particularly, to an interposer substrate and a method of fabricating the interposer substrate.
2. Description of Related Art
With the development in miniaturization for semiconductor packages, a typical printed circuit board (PCB) has smaller surface available to accommodate semiconductor packages. Therefore, a Package on Package (PoP) is developed having multiple packaging structures, each being stacked on top of the other in order to meet the high density requirement.
Traditional stacked packages are formed by stacking a semiconductor package via a plurality of solder balls such that it is electrically connected to another semiconductor package. However due to the limitation of the fabricating process, a certain size and distance must remain for the solder balls, as a result, the electrical external connection points would be reduced as only a limited area of the package is available, which leads to an increase in thickness of the overall package structure.
Referring to FIG. 1, in order to increase I/O number and meet the low-profile and compact-size requirements for the stacked package structures, an interposer substrate 10 is provided between a first semiconductor package 1A and a second semiconductor package 1B, and a first wiring layer 11 and a second wiring layer 12 are formed on the first surface and second surface of the interposer 10, respectively. The interposer substrate 10 has conductive vias 13 for electrically connecting the first wiring layer 11 with the second wiring layer 12.
FIGS. 2A-2F illustrate a method of fabricating an interposer substrate.
As shown in FIG. 2A, a core board 20 is provided. The core board 20 has a first surface 20a and an opposing second surface 20b. A plurality of vias 20c are formed on the core board 20 and penetrate the first and second surfaces 20a and 20b. A metal layer 21 is plated on the first surface 20a, the second surface 20b and the vias 20c of the core board 20.
As shown in FIG. 2B, the metal layer 21 on the first surface 20a and second surface 20b are patterned to form the first wiring layer 21a and second wiring layer 21b that are electrically connected through the metal layer in the vias (i.e., the conductive vias 21c). An insulating layer (a solder mask layer) 22 is formed on the first wiring layer 21a and the second wiring layer 21b, and a plurality of openings are formed on the insulating layer to expose a portion of the first wiring layer 21a and the second wiring layer 21b. 
As shown in FIG. 2C, a conductive layer 23 and a resist layer 24 are formed on the insulating layer 22 of the first surface 20a and the second surface 20b of the core board 20.
As shown in FIG. 2D, the resist layer 24 is patterned to form a plurality of openings to expose a portion of the second wiring layer 21b. An electroplating process is performed to form in the openings of the resist layer 24 a conductive material that is electrically connected with the second wiring layer 21b. 
As shown in FIG. 2E, the resist layer 24 and the conductive layer 23 covered by the resist layer 24 are removed to form an interposer substrate.
However, the method is complex and the cost thereof is high. The additionally disposed conductive layer is likely to deteriorate the electrical performance of the interposer substrate. In addition, the thickness of the interposer substrate is also limited, such that when the thickness is smaller (such as under 130 μm), it is difficult to be fabricated and damages could easily occur. Further the design of the wiring would be limited by, the line width/line space (L/S). The yield may be influenced when L/S is lower than 25/25 μm.
Hence, there is an urgent need to solve the foregoing problems encountered in the prior art.